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Posted by on Sep 22, 2012 in Hardware News |

Boulder: The future microprocessor NVIDIA HPC server

Boulder: The future microprocessor NVIDIA HPC server

Known for years that is working on his yet unreleased SoC Denver , and although there is still much to launch Denver, Nvidia is already working on another future SoC codenamed Echelon.

Nvidia has continually changed its plans for Denver, which at first would be a RISC can emulate x86 instructions, and then become an ARMv7 SoC, and recently (this year) plans changed again based on the new architecture (ARM 64-bit). Denver will end up being launched under the brand name T50 (Tegra 5).

Also Nvidia also working on another monstrous SoC known by its code name Echelon (here more about Echelon ), which is aimed at servers and supercomputers. But Echelon is not the only chip in which Nvidia is working, and apparently does not intend to rely forever on Xeon microprocessors / or Intel Itanium CPUs (and future APUs) AMD Opteron, and it plans to develop its own microprocessor, which is codenamed Boulder.

will consist of eight to 16 cores ARMv8 high performance together by interconnections and large memory bandwidth (possibly DDR4) and unified memory addressing between the microcomputer and future Nvidia cGPUs (Echelon or any future based GPU future architectures Maxwell or Einstein), technology that ioFX called, and is being developed in partnership between Nvidia and Fusion-io).

Unfortunately they are all data that we currently have on the future of Nvidia Boulder microprocessor, and whether they will focus only servers and supercomputers, or if there is also a consumer-oriented version.

Link: NVIDIA Boulder Project Revealed: Hides in Tegra’s GPU Competitor Group (Bright Side of News)

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