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Posted by on May 15, 2012 in Featured, Hardware Articles |

Meet the new AMD APUs Series A-2 nd generation “Trinity”


Today, finally debuted its highly anticipated new APU from AMD known by the code name Trinity, APU commercially called AMD A-Series 2nd generation that combine x86 cores based on the new micro-architecture Piledriver, the new Unified Northbridge (UNB) and VLIW4 graphics architecture, and initially sought to conquer the market for portable computers: notebooks and Ultrathins .

The new APU (Accelerated Processing Unit) “Trinity” are composed of a total of 1303 million transistors manufactured with the manufacturing process 32nm HKMG of Global Foundries, concentrated in an area of 246mm , area just greater than 228mm of its predecessor: the Llano APU. The APU Trinity initially available in three versions:

  • Trinity: APU with a TDP of 35W aimed at notebooks.
  • Trinity-LV: APU with a TDP of 25W Ultrathins aimed at high performance.
  • Trinity-ULV: APU with a TDP of 17W Ultrathins targets with more autonomy.

The APU Trinity along with AMD chipset known A70M “Hudson-M3″ FCH (Fusion Controller Hub), Comal make the new platform, a platform that will run for about a year and will be replaced sometime next year for the new Indus platform (APUs Kaveri + chipset A70M).

The AMD platform Comal (APU Trinity + chipset A70M).

Unfortunately we have to begin the technical part of this article with a description of each of the Trinity APU components, which work together make the vision of what AMD thinks will be the future of computing, a vision that the rest of the industry appears to be shared.

The Trinity die.

Before proceeding further we have prepared a table of specifications Trinity, comparing them to Llano, Zambezi, and the few known specifications of the successor of Zambezi Vishera known as:

The micro-architecture Piledriver

Piledriver is the code name for the modular architecture with processing CMT (Cluster Multi Threading) 2nd generation AMD architecture whose first example was the micro-architecture Bulldozer , which debuted last year with microprocessors Zambezi (AMD FX-Series) . Piledriver improves many of the weaknesses found in its predecessor, focusing on reducing energy consumption and leakage, while increasing the yield per cycle.

The module Piledriver.

Among the improvements brought about the new micro-architecture compared to Bulldozer Piledriver we have:

Improved cache scheme

AMD has improved significantly its cache scheme to improve the communication between the two ALUs (x86 cores Piledriver) and floating point unit (Flex-FP) of the new module Piledriver while increasing their performance, both caches 1 st and 2 nd level (L1 and L2) have lower latencies (although AMD does not specify exact figures), the L1 cache data doubles in size relative to the module Bulldozer, it seeks to reduce the number of cache misses (data not found in the L1) and thus improve performance.

Improvements to shared drives on the module

Like Bulldozer, Piledriver shares many hardware units between the two ALUs and FPU present in the module, which have been strengthened to improve performance, among the major improvements include:

  • New branch prediction unit (increases the efficiency of conditional branch prediction).
  • Enhanced Scheduler (instruction scheduler integer and floating point).
  • Pre-fetcher for improved hardware (high speed data acquisition).
  • New x86 decoder (4 per module, with support for new instructions FMA3 and F16C).
  • Instruction remove improved (faster execution of instructions out of order (OOO), division of integers and floating point).
  • Floating point unit improved Flex-FP (with higher performance and supports the new instruction set AVX1.1).

Unified NortBridge (UNB)

Eliminates the use of AMD HyperTransport bus, instead uses the PCIe bus as a means of interfacing with input / output, plus we have within the new integrated memory controller (IMC) DDR3-1866 (DDR3-1600 in portable version) with 1.25V memory support, which has been optimized to provide higher bandwidth to its modules and its graphics core Piledriver for the latter is designed an access channel called Radeon Memory Bus (RMB) , which connects the main memory controller with the memory controller in the IGP graphics.

UNB also supports unified x86 routing through IOMMU 2.0 interface, making it possible to access the memory address of the IGP from the x86 address space, but to use this feature requires Windows 8 and Linux distributions with kernel update .

The IGP / iGPU Thames

Thames is the new code name VLIW4 GPU architecture used in the APU Trinity, which consists of 6 units SIMD, each comprised of 8KB of L1, 16 VLIW4 shaders (which in turn are composed of 4 ALUs each ) and 4 texture units (TMU), giving us a total of 384 shader processors and 24 texture units, also has two double graphics memory controller channel (each consisting of two 32-bit drivers with 128kB of L2 each a “total 512kB L2″) each with 4 ROPs (8 ROPs in total).

The IGP Thames has a new tessellation unit with greater performance to that used in Llano, also includes the new AMD Media Accelerator Unit, which consists of the latest video engine Hardware accelerated (UVD “Unified Video Decoder”) and encoding unit hardware accelerated video (VCE “Video Codec Engine”) found in recent GPUs AMD Radeon HD 7000 Series architecture-based Core Graphic Next (GCN), also has 4 display drivers to be compatible with multi mode Eyefinity4-monitor (4 screens).

As computing capabilities accelerated GPU (GPGPU), Thames is able to provide a power of 736GFlops in single-precision calculations and 46GFlops in double-precision calculations (Llano does not support double precision calculations), which makes Thames in the first GPU to support the industry with double-precision calculations (the IGP Ivy Bridge only supports single-precision calculations).

There will be 3 variants of the core Thames:

  • Thames XT: 6 SIMDs/384 shaders/24 TMUs / 8 ROPs.
  • Thames Pro: 4 SIMDs/256 shaders/16 TMUs / 8 ROPs.
  • Thames LE: 3 SIMDs/192 shaders/12 TMUs / 8 ROPs.

AMD Dual Graphics 2.0

With Dual Graphics 2.0 technology will be possible to use the power of 3D graphics and computing the IGP to increase the performance of GPUs AMD Radeon HD 7000M dedicated series laptops that coincidentally share the same code name Trinity IGP: AMD Thames (Turks) “7600M/7500M Radeon HD Series” and Seymour (Caicos) “Radeon HD 7400M Series” as a sort of hybrid multi-GPU CrossFireX graphics between the two nuclei.

Turbo Core 3.0

Core Turbo new technology makes use of 3.0 Resonant Clock Mesh technology , which acts as a pendulum on both the electronic module as Piledriver on the graphics core to reduce consumption between 10% to 24%, this saving consumption is used by AMD to offer a more aggressive Turbo mode and a faster response time, which fits almost immediately and automatically to the type of task you are running both the microprocessor and its graphics core, offering the highest return possible without sacrificing the autonomy of the team.

The new socket

The new APU Trinity because of its profound changes introduce new socket: FS2 (FS1r2/FS1 +) and FP2, the former will be used by Trinity in its version for notebooks (35W TDP), while FP2 (BGA) variants will be used in Trinity -LV and ULV-Ultrathins Trinity. AMD has not been clear with regard to backward compatibility with the socket used by FM1 Llano APU, but we assume that having replaced the HyperTransport bus for the new PCIe-based interfaces, will not be possible to use an APU in Trinity FS1 old socket.

The first APU AMD A-Series 2 nd Generation

Today AMD has five A-Series APUs 2 nd generation based in Trinity, which are present in a wide variety of notebooks and Ultrathins. AMD promises that they will offer better overall performance than its popular Llano APU, a promise that we will see in our review of one of the first laptops based on Trinity.

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