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Posted by on May 29, 2012 in Hardware News |

More details on the future AVX instruction set 2.0

More details on the future AVX instruction set 2.0

The instruction set AVX was introduced microprocessors launched from 2011 (Intel Core 2 nd generation “Sandy Bridge” and FX of 1 generation “Zambezi”), and is expected to microprocessors next year to incorporate the new game 2.0 AVX instructions.

The APUs AMD A Series of 2 nd generation “Trinity” incorporate new instruction sets AVX 1.1 (which actually might call unofficial or partial) and FMA3, two developments that incorporate microprocessors based on new micro- architectures to be released next year: (Intel) and (AMD).

AVX 2.0 will provide new capabilities such as support for operations with 256-bit integers, addressing Gather / Scatter , and (Fused Multiply-Add), which have records for three operands.

FMA3 (three entries) is considered a destructive instruction set, as for example if we have (A * B) + C = D, the result (D), rather than written to a separate record, over-write any of the 3 operands (A / B / C), which does not happen in the instruction set FMA4 (this game has 4 records), set of instructions present in AMD microprocessors based on Bulldozer micro-architecture .

FMA3 destructive mode may penalize performance, because if another operation requires either operand, this data must be reloaded, although the advantage may be mentioned that requires fewer transistors FMA3 FMA4, so it will be very soon FMA4 into oblivion, despite its obvious advantages.

AVX 2.0 promises to deliver performance per cycle than twice that of AVX 1.0, plus also serve to increase the performance of integer operations, but the evolution of instructions not stop with AVX 2.0, since the micro-architectures of 2015: (Intel) and (AMD) will offer new sets of instructions detailed yet offer even greater benefits.

Link: AVX2 im Detail: Der erweiterte Befehlssatz für Ivy-Bridge-Nachfolger Haswell (PC Games Hardware)

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