Skylake will be the first Intel micro-architecture with four integrated PCIe controller
Future xeon microprocessors based Haswell microarchitecture: Haswell-EP/EN expected improvements introduced as DDR4 memory support, but although these chips coming next year, of course we get some details of his successors:
Xeon CPUs “Broadwell-EP/EN” (2015)
Haswell-EP/EN successor, probably use the same socket LGA 2011-3 used by his predecessor. It will be manufactured using the 14nm manufacturing process and apparently, outside the smaller manufacturing process introduce the new AVX 3.0 instruction set.
cGPUs Xeon Phi “Knights Landing” (2015)
Successor of the current Xeon Phi “Knights Corner”. Out of the initially revealed by Intel, Knights Landing will own main memory and surprisingly DDR4 will be the first product released intel AVX instruction set 3.1.
It should be mentioned that Knights Corner has up to 61 x86 cores equipped with wide vector units-16, which are exploited via standard OpenCL API, so its native support for AVX 3.1 instruction set leads us to assume that these vector units within a very bit vector units will replace traditional competitor promise promised remember many years ago.
In terms of performance we have to have a power calculation in single precision from 14 to 16 gigaflops per watt and power calculation in double precision initially close to 3 teraflops, a figure that exceeds the 3 teraflops in future editions.
Xeon CPUs “Skylake-EP/EN” (2016)
Broadwell-EP/EN successor, which will be manufactured with a 14nm manufacturing process. Among the new features we support the new AVX instruction set 3.2 and a PCI Express (PCIe) 4.0.
Given the changes that incorporates this microprocessor, is quite likely to use a new socket.
Link: Skylake: Intels 14-Nanometer CPUs kommen mit-PCI-Express 4, DDR4 und SATA-Express (PC Games Hardware)
.Tags: 2 °, AVX 3, AVX 3.1, Broadwell, Broadwell-EN, Broadwell-EP, cGPU, CPU, intel, Knights Landing, PCIe 4.0, PCIe4, Skylake, Skylake-EN, Skylake-EP, xeon