The Intel Haswell microarchitecture: Part 3
The IDF 2012 event began yesterday, and intel continues giving us new details of its Haswell microarchitecture. Before reading this third and final part, we recommend you read our two previous articles ( Part 1 and Part 2 ).
Transactional Synchonization eXtensions (TSX)
TSX could define as new instructions aimed at increasing the performance of multi-threaded applications, to improve the synchronization between different threads spread among multiple microprocessor cores, automatically detecting and in “real time” data conflicts between the threads (elided Locks) and in regions associated cache and DRAM (Restricted Transactional memory) that act directly on the data records.
This is achieved with a physical unit Lock Elision (Hardware Lock Elision), which is responsible for this task entirely in hardware, greatly reducing the number of calculations wasted in data synchronization (less runtime), while providing significant savings in the internal bandwidth.
Advanced Vector Extensions 2.0 (AVX2)
With new two 128-bit FMA units per core that has Haswell, Intel promises to nearly double the performance of vector operations on integers (single precision or SP) regarding Ivy Bridge to be able to run 256-bit SSE instructions (Ivy Bridge is limited to 128 bits). This is achieved by adding an integer processing unit (ALU) to 128-bit registers of the units FMA.
fma3 (Fused Multiply-Add)
Haswell FMA units are also capable of executing instructions FMA3, which are designed to deliver superior performance in floating point operations, it is capable of running eight single-precision operations or four double precision (DP) per cycle.
This is achieved thanks to the ability to perform multiplication and addition operations merged into a single operation (for example: (a * b) + c), may play a total of 20 variations applied to both positive and negative numbers.
Other new instructions
Among other brings new Haswell instructions include:
- Gather Instructions (Dword data collection “SP” and Qword “DP” in a vector register).
- Bit Manipulation Instructions “BMI” (15 new instructions dedicated to handling arbitrary bit fields).
- MOVBE (Swap the order of the data “bytes” stored in the load and store units “load / store”).
The new games Haswell instructions may be used by future applications compiled with Intel Compiler 13.0 compilers, GCC 4.8 and Visual Studio 2012 and above.
The integrated memory controller (IMC)
Apparently there will not be too many changes to the integrated memory controller in Haswell, like this in Ivy Bridge, Haswell has an integrated memory controller (Integrated Memory Controller “IMC”) dual channel frequency which is even kept secret by Intel, but most likely it’s DDR3-1866 or DDR3-1600.
The integrated controller PCIe
As in the third generation core architecture “Ivy Bridge” Haswell has a PCIe 3.0 integrated controller, this controller includes a total of 16 lines dedicated to graphics adapters PCIe (video card) that can be used in the 1x16X modes or 2x8X or 8X/4x/4x, supporting multi-GPU configurations 3-Way SLI (Nvidia) or CrossFireX (AMD).
The new chipset (PCH) 8 Series
In terms of features there is much to talk about new chipsets 8 Series “Lynx Point” Intel will be the first except that Intel chipsets manufactured with 32nm manufacturing process (chipsets 5, 6 and 7 Series are made with 65nm manufacturing process).
The new chipsets maintain an internal bus for direct communication with the bus DMI (Direct Media Interface) present from the first generation Core microprocessors (Nehalem).
The Intel microprocessors based on Haswell
As in the other Intel micro-architecture, there will be many microprocessors based on the Haswell microarchitecture, whose code names are:
- Haswell-DT (desktop socket LGA 1150).
- Haswell-MB (laptops).
- Haswell-ULT (ultrabooks).
- Haswell-E (desktop socket LGA 2011 “not backwards compatible with the current LGA 2011″).
- Haswell-EN (mono-socket servers).
- Haswell-EP (dual socket servers).
- Haswell-EX (quad socket servers).