The new micro-architecture AMD Jaguar
The Future is Fusion, is the slogan that promotes AMD, which does not rest on his career to his new approach: balanced products targeting the most profitable segments of the market, and one of the most profitable teams is the low-power with high autonomy, very important factor in portable computers, especially in its most lightweight and economical.
Earlier last year made their appearance first amd fusion APU, the hitherto popular E-Series APU (AMD E-350 and other members of the AMD Brazos platform), the first products based on the highly anticipated then micro -architecture Bobcat , and that became a nightmare for Intel Atom microprocessor line, which can not compete with their performance in any of their areas (or as CPU or as IGP).
AMD recently launched its new platform Brazos 2.0 (E2-1000 Series APUs), which is also based on the Bobcat microarchitecture, but by the end of next year Intel readies his future platform Baytrail formed by the new Atom chips based Valleyview Silvermont new micro-architecture, which will challenge all aspects Bobcat (CPU as well as GPU), and most likely end up beating Brazos 2.0 (Bobcat microarchitecture).
AMD does not plan to stay waiting for Silvermont defeat Bobcat, so that already announced its successor: the new jaguar micro-architecture, which aims to maintain its lead in this segment. If they succeed or not is a matter that we can see just the last months of 2013.
The Jaguar AMD microarchitecture
A few weeks ago I drew my own speculations on the micro-architecture jaguar , but I was far from being right. Jaguar is based on the k10.6 microarchitecture (used in the cores of the APU Llano Husky anyway K10.5 more advanced than the one based on Bobcat), but with new refinements taken from the modern modular architectures AMD (Bulldozer, Piledriver, Steamroller and Excavator), although obviously redesigned to focus on a low power consumption.
K10.6 microarchitecture evolved and taken to limit
Being based on the K10.6 microarchitecture, Jaguar is comprised of independent cores (we will call Jaguar nuclei), each consisting of a core x86 integer, L1 (I / D instructions and data) and a new, powerful floating point unit “FPU” of 128 bits (the Bobcat FPU is 64 bits) supports 128-bit AVX instructions, to execute 256-bit AVX instructions should do it in two passes, but considering that this is a chip Low consumption is unlikely to be allocated to this type of instruction.
The similarities end there K10.6 is because AMD micro-architecture redesign to give it the present advanced instruction sets in current microprocessors AMD FX-Series “Bulldozer” as: SSE 4.1, SSE 4.2, AES (encryption), CLMUL, MOVBE, AVX 1.0, xSave / XSAVEOPT, F16C and BMI; Jaguar brings no FMA4 instructions, a factor which is not surprising considering that is aimed at low-power chips.
Jaguar cores share an L2 cache unit for data called AMD Shared Cache Unit (SCU), which consists of four banks of 512K each (2MB in total) and is capable of operating at half the frequency chip, only running at full speed when a chip requires intensive application, all managed by an L2 interface, which communicates directly with the first level L1 cache, a scheme that should save many transistors and also simplifies chip design, and which somehow reminds us that AMD is not abandoning its trend towards modular hardware design shared.
A higher yield per cycle (IPC)
AMD claims to have made many improvements to the microarchitecture Bobcat Jaguar regarding, among them are a new division unit fast hardware (based on the present in Llano APU), branch prediction units, prefetcher, fetch and decode improved, more resources for out of order execution, schedulers more robust improvements in L1 cache (lower latencies), which now have a better intercommunication with the FPU.
The improvements mentioned in the previous paragraph, allow Jaguar has a yield per cycle (IPC) over 15% higher than the Bobcat, yet with lower consumption at the same frequency, allowing you to provide operating frequencies up 10% higher, ie Jaguar products could have dual core running at 2GHz and a yield about 30% higher than the future AMD E2-1800 APU . Not bad for a low-power chip.
Another area in which AMD claims to have worked is improved support for virtualization, greatly improving its performance in this area, which suggests that we could have designed a Jaguar to produce not only focused SoCs APUs and equipment desktop and portable low power, but also for use in future products aimed at low-power servers , which could come under the Opteron and FirePro brand.
The Jaguar computer unit
AMD calls the combination of the four cores Jaguar and shared L2 cache unit (SCU) Jaguar Computer Unit (CU or Compute Unit), this unit will be accompanied by a renewed IGP, which AMD has not yet provided details but assume that will be based on the architecture used in graphic VLIW4 Trinity APU and the AMD Radeon HD 6900 GPU Series, or perhaps in a cropped version of the Graphics Core Next architecture (Radeon HD 7000).
The memory controller of Jaguar
As for the integrated memory controller, Jaguar has an improved memory controller single-channel (single channel) of 40 bits, with maximum support 1TB (1000GB) of memory installed, but still unknown frequency.
Future Jaguar based APU
The first products based on AMD’s new Bobcat micro-architecture will be the Kabini APU and Temash SoC , which will be manufactured with the 28nm manufacturing process (still do not know if the manufacturer of such chips will Global Foundries or TSMC), and will be released sometime next year.
—–Tags: 28nm, amd, compute unit, consumption, fusion, improvement, ipc, jaguar, Jaguar core, k10.6, low, micro-architecture, module, performance, SCU, Shared Cache Unit, Virtualization